Routing and tuning DDR4 interfaces in 1/4th the time

Routing and tuning DDR4 interfaces in 1/4th the time


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Bill Munroe, principal PCB designer in Cavium’s Post-Silicon Group, talks about how the Allegro TimingVision technology helped his team achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems. Routing boards with high-speed interfaces had been a time-consuming, manual process at Cavium. To alleviate scheduling pressures without sacrificing quality of their multi-layer boards, the San Jose, CA, semiconductor company automated the process with the Cadence® Allegro® TimingVision environment. In this 3-minute video, Bill Munroe, principal PCB designer in the company's Post-Silicon Group, talks about how the technology helped his team achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems. After watching the video, learn more about the Allegro TimingVision environment by clicking the button. More info on Allegro TimingVision