HDI Via Design: Planning the Energy Pipelines
Many high-speed and high-density failures traced to SI, PI, EMI and thermal issues originate in one place: the via field. Even when routing and components are correct, poorly designed HDI vias silently degrade performance through return path discontinuities, parasitics, and current crowding.
Signal integrity and EMC expert Dan Beeker returns with a practical physics-based deep dive into HDI via design. Join us for this live webinar and explore the practical engineering realities of using HDI vias in modern designs. This session focuses on how vias behave as 3D electromagnetic structures and how their geometry, reference transitions, and anti-pads directly control signal integrity, PDN impedance, and heat flow.
This session will cover:
- How return currents actually flow through HDI via transitions.
- How to design effective transmission lines and via structures.
- How to prevent reference plane breaks and loop inductance at layer changes.
- Suggestions for improving power delivery and thermal management.
If you design dense, high-speed boards, this webinar will change how you think about vias and help you avoid costly SI, PI, and EMI surprises in your next layout.
Unable to attend live? Register anyway and we will send you the recording so you can watch it at your convenience. Clicking the link will redirect you to Cadence’s registration page
